The present invention relates to a vertical semiconductor structure that facilitates realizing both a high breakdown voltage and a high current capacity in insulated gate field effect transistors (MOSFET""s), insulated gate bipolar transistors (IGBT""s), bipolar transistors, diodes and such semiconductor devices. The present invention also relates to a method of manufacturing the semiconductor device with such a vertical semiconductor structure.
Semiconductor devices may be roughly classified as lateral semiconductor devices wherein electrodes are arranged on a major surface and vertical semiconductor devices wherein electrodes are distributed on both major surfaces opposing each other. When the vertical semiconductor device is ON, a drift current flows in the expansion direction of a drift layer, which becomes depleted by the reverse bias voltage when the vertical semiconductor device is OFF. FIG. 19 is a cross section of a conventional planar n-channel vertical MOSFET. Referring now to FIG. 19, this vertical MOSFET includes a drain electrode 18; an n+-type drain layer 11 with low resistance, to which drain electrode 18 is in electrical contact; a highly resistive nxe2x88x92-type drift layer 12 on n+-type drain layer 11; a p-type base region 13a selectively formed in the surface portion of nxe2x88x92-type drift layer 12; a heavily doped n+-type source region 14 selectively formed in p-type base region 13a; a gate electrode layer 16 above the extended portion of p-type base region 13a extended between n+-type source region 14 and nxe2x88x92-type drift layer 12; a gate oxide film 15 between gate electrode layer 16 and the extended portion of p-type base region 13a; a source electrode 17 in common contact with the surfaces of n+-type source region 14 and p-type base region 13a; and a drain electrode 18 on the back surface of n+-type drain layer 11.
In the vertical semiconductor device as shown in FIG. 19, highly resistive nxe2x88x92-type drift layer 12 works as a region for making a drift current flow vertically when the MOSFET is in the ON-state. Highly resistive nxe2x88x92-type drift layer 12 is depleted when the MOSFET is in the OFF-state, resulting in a high breakdown voltage of the MOSFET. Shortening the current path in highly resistive nxe2x88x92-type drift layer 12 is effective for substantially reducing the on-resistance (resistance between the drain and the source) of the MOSFET, since the drift resistance is lowered. However, the short current path in nxe2x88x92-type drift layer 12 causes breakdown at a low voltage, since the expansion width of the depletion layer that expands from the pn-junction between p-type base region 13a and nxe2x88x92-type drift layer 12 is narrowed and the electric field strength soon reaches the maximum (critical) value for silicon. In a semiconductor device with a high breakdown voltage, the characteristically thick nxe2x88x92-type drift layer 12 causes high on-resistance and therefore, losses increase. In short, there exists a tradeoff between the on-resistance and the breakdown voltage of the MOSFET. This tradeoff between the on-resistance and the breakdown voltage also exists in other semiconductor devices such as IGBT""s, bipolar transistors and diodes. The tradeoff between the on-resistance and the breakdown voltage is also present in lateral semiconductor devices, in which the flow direction of the drift current in the ON-state of the devices is different from the expansion direction of the depletion layer in the OFF-state of the device.
EP0053854, U.S. Pat. Nos. 5,216,275, 5,438,215 and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose semiconductor devices that include a drift layer including heavily doped n-type regions and p-type regions alternately laminated with each other to solve the foregoing problems. The alternately laminated n-type regions and p-type regions are depleted to bear the breakdown voltage in the OFF-state of the device.
FIG. 20 is a cross section of a part of the vertical MOSFET according to an embodiment of U.S. Pat. No. 5,216,275. The vertical MOSFET of FIG. 20 is different from the vertical MOSFET of FIG. 19 in that the vertical MOSFET of FIG. 20 includes a drift layer 22, that is not single-layered, but consists of n-type drift regions 22a and p-type drift regions 22b alternately laminated with each other. In the figure, there is a p-type base region 23a, an n+-type source region 24, a gate electrode 26, a source electrode 27, and a drain electrode 28.
Drift layer 22 is formed in the following manner. First, a highly resistive n-type layer is grown epitaxially on an n+-type drain layer 21. The nxe2x88x92-type drift regions 22a are formed by etching the highly resistive n-type layer to form trenches down to n+-type drain layer 21. Then, p-type drift regions 22b are formed by epitaxially growing p-type layers in the trenches.
Hereinafter, the semiconductor device, including an alternating conductivity type drift layer that makes a current flow in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as a xe2x80x9csemiconductor device with an alternating conductivity type layer.xe2x80x9d
The dimensions described in U.S. Pat. No. 5,216,275 are as follows. When the breakdown voltage is put in VB, the thickness of the drift layer 22 is 0.024VB1.2 (xcexcm). When n-type drift region 22a and p-type drift region 22b have the same thickness b and the same impurity concentration, the impurity concentration is 7.2xc3x971016VBxe2x88x920.2/b (cmxe2x88x923). If VB is 800 V and b xcexcm, the drift layer 22 will be 73 xcexcm in thickness and the impurity concentration 1.9xc3x971016 cmxe2x88x923. Since the impurity concentration for the single-layered drift layer is around 2xc3x971014 cmxe2x88x923, the on-resistance is reduced. However, when using conventional epitaxial growth techniques, it is difficult to bury a good quality semiconductor layer in such a narrow and deep trench (with a large aspect ratio).
The tradeoff between the on-resistance and the breakdown voltage is also commonly encountered in lateral semiconductive devices. The foregoing references, EP0053854, U.S. Pat. No. 5,438,215 and Japanese Unexamined Laid Open Pat. Application H09(1997)-266311, disclose lateral semiconductor devices with an alternating conductivity type layer and methods, common to the lateral semiconductor devices and vertical semiconductor devices, for forming the alternating conductivity type layer which employ selective etching technique for digging trenches and epitaxial growth techniques for filling the trenches. In manufacturing the lateral semiconductor device, it is relatively easy to employ selective etching techniques and epitaxial growth techniques to form an alternating conductivity type layer, since thin epitaxial layers are laminated one by one.
However, it is difficult to employ the selective etching technique for digging trenches and using an epitaxial growth technique for filling the trenches in manufacturing the vertical semiconductor devices with alternating conductivity type layer as explained with reference to U.S. Pat. No. 5,216,275. Japanese Unexamined Laid Open Patent Application H09(1997)-266311 describes the nuclear transformation by a neutron beam and such radioactive beams. However, such nuclear transformation processes require large facilities and cannot be used easily.
In view of the foregoing, it is an object of the invention to provide a semiconductor device with alternating conductivity type layer that reduces the tradeoff relation between the on-resistance and the breakdown voltage.
It is another object of the invention to provide a semiconductor device with an alternating conductivity type layer and with a high breakdown voltage that facilitates increasing the current capacity by reducing the on-resistance. It is still another object of the invention to provide a method for manufacturing such a semiconductor device with alternating conductivity type layer easily and with excellent mass-productivity.
According to an aspect of the invention, there is provided a semiconductor device including: a layer with low electrical resistance; a semiconductive substrate region having a first surface contacting the layer with low electrical resistance and a second surface; one or more electrodes on the second surface of the semiconductive substrate region; and an electrode on the surface of the layer with low electrical resistance not contacting the semiconductive substrate layer; the semiconductive substrate region providing a current path when the semiconductor device is ON and being depleted when the semiconductor device is OFF; the semiconductive substrate region including regions of a first conductivity type and regions of a second conductivity type; the regions of the first conductivity type and the regions of the second conductivity type being extended substantially in parallel to each other vertically and arranged alternately with each other horizontally; each of the regions of the first conductivity type including a plurality of second buried regions of the first conductivity type aligned vertically at a predetermined pitch; each of the regions of the second conductivity type including a plurality of first buried regions of the second conductivity type aligned vertically at the predetermined pitch.
Advantageously, the first buried regions and the second buried regions are located at almost the same depths from the surface of the semiconductive substrate region.
Advantageously, the second buried regions are located near the midpoints between the depths, at which the first buried regions are located, from the surface of the semiconductive substrate region.
Since the above described semiconductive substrate region is depleted in the OFF-state of the semiconductor device, the impurity concentrations in the first buried regions or the second buried regions can be increased. Thus, the on-resistance is lowered. Advantageously, the spacing I1 between the centers of the adjacent first buried regions aligned vertically is from 2 to 10 xcexcm. When the spacing I1 exceeds 10 xcexcm, heat treatment should be conducted for an extended period of time to make the first buried regions or the depletion layers which expand from the first buried regions continue to each other. When the spacing I1 is less than 2 xcexcm, growth of the highly resistive layer and impurity doping by ion implantation should be repeated several times, resulting in increased manufacturing steps which are generally undesirable for mass-production.
Advantageously, a relational expression 0.5dxe2x89xa6I1xe2x89xa62d holds for the spacing I1 between the centers of the adjacent first buried regions aligned vertically and the average spacing 2d between the centers of the horizontally adjacent first buried regions.
If one assumes that the impurities diffuse evenly in all directions, the upper buried regions and the lower buried regions continue to each other and, at the same time, the first buried regions and the second buried regions continue to each other, then I1 should approximately equal d. If I1 differs significantly from d, heat treatment should be conducted for an extended period of time to make the upper buried regions and the lower buried regions continue to each other after the first buried regions and the second buried regions have continued to each other or to make the first buried regions and the second buried regions continue after the upper buried regions and the lower buried regions have continued to each other. Thus, I1 being significantly different from d is not desirable from the view point of efficient manufacturing. Therefore, the desirable range for I1 is between 0.5d and 2d.
Advantageously, a relational expression I0 less than I1 holds for the spacing I0 between the upper surface of the layer with low electrical resistance and the center of the lowermost first buried region and the spacing I1 between the centers of the adjacent first buried regions aligned vertically.
If I0 is close to I1, the highly resistive region remains with about half the original thickness left. The remaining highly resistive region causes increased on-resistance. Therefore, it is preferable for I0 to be much smaller than I1.
Advantageously, the first buried regions aligned vertically continue to each other.
Since the first buried regions of the second conductivity type are disposed to expand depletion layers into the second buried regions of the first conductivity type, the vertically aligned first buried regions can be separated as long as the spaces between them are narrow enough to make the depletion layers continuous. However, the first buried regions surely work as intended when they continue to each other.
Advantageously, the second buried regions aligned vertically continue to each other.
Since the vertically aligned second buried regions provide a drift current path, the highly resistive layer between them results in increased on-resistance. Therefore, it is desirable for the vertically aligned second buried regions to continue to each other. Since the second buried regions of the first conductivity type are disposed to expand the depletion layers into the first buried regions of the second conductivity type, the vertically aligned second buried regions can be separated as long as the spaces between them are narrow enough to make the depletion layers continuous. The second buried regions also work as intended when they continue to each other.
Advantageously, the first buried regions and the second buried regions are formed with stripes extending horizontally. Advantageously, the first buried regions are formed with a lattice or a honeycomb extending horizontally, and the second buried regions are in the horizontally lattice-shaped first buried regions or in the bores of the horizontally honeycomb-shaped first buried regions. Alternatively, the second buried regions are formed with a lattice or a honeycomb extending horizontally, and the first buried regions are in the horizontally lattice-shaped second buried regions or in the bores of the horizontally honeycomb-shaped second buried region. Advantageously, the first buried regions are distributed on the lattice points of a rectangular lattice, a triangular lattice or a hexagonal lattice, and the second buried region is between the horizontally adjacent first buried regions. Alternatively, the first buried regions are distributed on the lattice points of a rectangular lattice, a triangular lattice or a hexagonal lattice, and the second buried region is in the center of the unit lattice of the rectangular lattice, the triangular lattice or the hexagonal lattice.
Any patterns and configurations are acceptable so long as the selected pattern facilitates expanding the depletion layers into the first buried regions and the second buried regions. Advantageously, the average spacing 2d between the centers of the horizontally adjacent first buried regions is from 2 to 20 xcexcm.
When an impurity is diffused for about 0.3 xcexcm from a window opened in the surface of the epitaxial layer of about 0.4 xcexcm in width, which is the limit of the conventional lithographic techniques, 2d is about 2 xcexcm. When 2d exceeds 20 xcexcm, the impurity concentrations should be around 2xc3x971015 cmxe2x88x923, to deplete the first buried regions and the second buried regions by applying a voltage of around 300V. When the impurity concentration is about 2xc3x971015 cmxe2x88x923, it is not effective at reducing the on-resistance.
According to another aspect of the invention, the first buried regions and the second buried regions are formed by diffusing respective impurities into a highly resistive layer laminate epitaxially grown on the layer with low electrical resistance. By the above described manufacturing method, the semiconductor device with an alternating conductivity type layer is easily manufactured without requiring trenches with a high aspect ratio and filling the trenches with buried regions. In the semiconductor device manufactured by the method according to the invention, impurity concentration distributions are caused in the first buried regions and the second buried regions by the impurity diffusion from limited impurity sources.